\doxysection{SAI\+\_\+\+Block\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_s_a_i___block___type_def}{}\label{struct_s_a_i___block___type_def}\index{SAI\_Block\_TypeDef@{SAI\_Block\_TypeDef}}
\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_a_i___block___type_def_a8935f3f22c733c1cb5a05cecf3cfa38c}{CR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_a_i___block___type_def_ad9976416e6199c8c1f7bcdabe20e4bd2}{CR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_a_i___block___type_def_a56001d4b130f392c99dde9a06379af96}{FRCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_a_i___block___type_def_aaef957d89b76c3fa2c09ff61ee0db11d}{SLOTR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_a_i___block___type_def_aefcc864961c2bb0465e2ced3bd8b4a14}{IMR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_a_i___block___type_def_ad1505a32bdca9a2f8da708c7372cdafc}{SR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_a_i___block___type_def_a52dffdfbe572129cc142023f3daeeffe}{CLRFR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_a_i___block___type_def_a9217ce4fb1e7e16dc0ead8523a6c045a}{DR}}
\end{DoxyCompactItemize}


\label{doc-variable-members}
\Hypertarget{struct_s_a_i___block___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_s_a_i___block___type_def_a52dffdfbe572129cc142023f3daeeffe}\index{SAI\_Block\_TypeDef@{SAI\_Block\_TypeDef}!CLRFR@{CLRFR}}
\index{CLRFR@{CLRFR}!SAI\_Block\_TypeDef@{SAI\_Block\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CLRFR}{CLRFR}}
{\footnotesize\ttfamily \label{struct_s_a_i___block___type_def_a52dffdfbe572129cc142023f3daeeffe} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SAI\+\_\+\+Block\+\_\+\+Type\+Def\+::\+CLRFR}

SAI block x clear flag register, Address offset\+: 0x1C \Hypertarget{struct_s_a_i___block___type_def_a8935f3f22c733c1cb5a05cecf3cfa38c}\index{SAI\_Block\_TypeDef@{SAI\_Block\_TypeDef}!CR1@{CR1}}
\index{CR1@{CR1}!SAI\_Block\_TypeDef@{SAI\_Block\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR1}{CR1}}
{\footnotesize\ttfamily \label{struct_s_a_i___block___type_def_a8935f3f22c733c1cb5a05cecf3cfa38c} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SAI\+\_\+\+Block\+\_\+\+Type\+Def\+::\+CR1}

SAI block x configuration register 1, Address offset\+: 0x04 \Hypertarget{struct_s_a_i___block___type_def_ad9976416e6199c8c1f7bcdabe20e4bd2}\index{SAI\_Block\_TypeDef@{SAI\_Block\_TypeDef}!CR2@{CR2}}
\index{CR2@{CR2}!SAI\_Block\_TypeDef@{SAI\_Block\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR2}{CR2}}
{\footnotesize\ttfamily \label{struct_s_a_i___block___type_def_ad9976416e6199c8c1f7bcdabe20e4bd2} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SAI\+\_\+\+Block\+\_\+\+Type\+Def\+::\+CR2}

SAI block x configuration register 2, Address offset\+: 0x08 \Hypertarget{struct_s_a_i___block___type_def_a9217ce4fb1e7e16dc0ead8523a6c045a}\index{SAI\_Block\_TypeDef@{SAI\_Block\_TypeDef}!DR@{DR}}
\index{DR@{DR}!SAI\_Block\_TypeDef@{SAI\_Block\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DR}{DR}}
{\footnotesize\ttfamily \label{struct_s_a_i___block___type_def_a9217ce4fb1e7e16dc0ead8523a6c045a} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SAI\+\_\+\+Block\+\_\+\+Type\+Def\+::\+DR}

SAI block x data register, Address offset\+: 0x20 \Hypertarget{struct_s_a_i___block___type_def_a56001d4b130f392c99dde9a06379af96}\index{SAI\_Block\_TypeDef@{SAI\_Block\_TypeDef}!FRCR@{FRCR}}
\index{FRCR@{FRCR}!SAI\_Block\_TypeDef@{SAI\_Block\_TypeDef}}
\doxysubsubsection{\texorpdfstring{FRCR}{FRCR}}
{\footnotesize\ttfamily \label{struct_s_a_i___block___type_def_a56001d4b130f392c99dde9a06379af96} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SAI\+\_\+\+Block\+\_\+\+Type\+Def\+::\+FRCR}

SAI block x frame configuration register, Address offset\+: 0x0C \Hypertarget{struct_s_a_i___block___type_def_aefcc864961c2bb0465e2ced3bd8b4a14}\index{SAI\_Block\_TypeDef@{SAI\_Block\_TypeDef}!IMR@{IMR}}
\index{IMR@{IMR}!SAI\_Block\_TypeDef@{SAI\_Block\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IMR}{IMR}}
{\footnotesize\ttfamily \label{struct_s_a_i___block___type_def_aefcc864961c2bb0465e2ced3bd8b4a14} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SAI\+\_\+\+Block\+\_\+\+Type\+Def\+::\+IMR}

SAI block x interrupt mask register, Address offset\+: 0x14 \Hypertarget{struct_s_a_i___block___type_def_aaef957d89b76c3fa2c09ff61ee0db11d}\index{SAI\_Block\_TypeDef@{SAI\_Block\_TypeDef}!SLOTR@{SLOTR}}
\index{SLOTR@{SLOTR}!SAI\_Block\_TypeDef@{SAI\_Block\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SLOTR}{SLOTR}}
{\footnotesize\ttfamily \label{struct_s_a_i___block___type_def_aaef957d89b76c3fa2c09ff61ee0db11d} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SAI\+\_\+\+Block\+\_\+\+Type\+Def\+::\+SLOTR}

SAI block x slot register, Address offset\+: 0x10 \Hypertarget{struct_s_a_i___block___type_def_ad1505a32bdca9a2f8da708c7372cdafc}\index{SAI\_Block\_TypeDef@{SAI\_Block\_TypeDef}!SR@{SR}}
\index{SR@{SR}!SAI\_Block\_TypeDef@{SAI\_Block\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SR}{SR}}
{\footnotesize\ttfamily \label{struct_s_a_i___block___type_def_ad1505a32bdca9a2f8da708c7372cdafc} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SAI\+\_\+\+Block\+\_\+\+Type\+Def\+::\+SR}

SAI block x status register, Address offset\+: 0x18 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
